The present invention generally relates to a method of manufacturing semiconductor devices, and more particularly relates to a method of manufacturing low power dissipation semiconductor power devices.
Some of the low power dissipation semiconductor power devices of the prior art have a junction structure (hereafter referred to as “super junction”) consisting of a vertical junction group where a first conductivity-type region and a second conductivity-type region are alternatively arranged vertically to the surface of a silicon substrate.
There is a prior method of creating such super junction structure by repeating N− epitaxial growth and ion implantation. FIG. 1 provides a brief explanation of this manufacturing process. In FIG. 1, a flow of the manufacturing process is shown in the right-hand part and cross sections of the silicon substrate at each step in the left-hand part.
As shown in FIG. 1, an N+ silicon substrate 101 is prepared and on that an N− epitaxial layer 102 is grown. Then boron-ions are implanted by the use of an ion implantation mask (not shown) to form P+ regions 103 in the N− epitaxial layer 102. Subsequently, by the use of an inverted mask of the ion implantation mask, phosphorous ions are implanted in a region adjacent to the P+ regions 103 to form N+ regions 104.
These ion-implanted regions are activated by annealing (not shown) to provide the P+ regions 103 and N+ regions 104. Annealing can be performed either after each ion implantation or after all the implantations have been completed. In this way, a PN junction plane is formed as part of a super junction consisting of PN junctions vertically arranged to the surface of an epitaxial layer.
Next, another N− epitaxial layer 102 is grown and, as shown in the right-hand part of FIG. 1, the steps from boron implantation to N− epitaxial growth are repeated. Then a vertical super junction is formed where PN-junction planes are alternatively created in the vertical direction to the wafer surface.
The N+ silicon substrate 101, which was used at an early step, will be a drain region of the low power dissipation semiconductor power device. Since the manufacturing method to be employed in the processes after the formation of a super junction is described later in FIG. 6D, detail explanation is not given here.
If a low power dissipation semiconductor power device having this super junction structure is manufactured to which high voltages are applied, since drain junction planes are formed by P+ and N+ regions that extend vertically to the wafer surface and a current path is created in the N+ layer in the inner bulk region of the silicon substrate, the low power dissipation semiconductor power device of NMOS-type shows a low ON resistance and a high drain withstand voltage.
A shortcoming in the above prior art is that such manufacturing method of repeating the epitaxial growth process to create low power dissipation semiconductor power devices is costly, difficult to implement and not suitable for mass production.